Rack is OCP's Tech Day programming on the rack as the unit of AI compute. Open racks heading to 1MW, more than one accelerator in the same fleet, scale-up networking, liquid cooling and 800 VDC power, from the hyperscaler and silicon engineers who write the open specs.
The Rack track is OCP Tech Day, programmed by the Open Compute Project, on designing the 1MW rack: open racks, silicon diversity, AI-native servers, in-rack scale-up interconnect, in-rack cooling and in-rack power distribution. Sessions are confirmed by OCP; these are the topics on the agenda.
The rack frame is now a load-bearing specification. Meta's Open Rack Wide (ORW) design is 1,200 mm wide and rated for at least 4,700 kg of payload, against 1,400 kg for an ORv3 high-power rack; the ORW base specification from Meta and Rittal reached v1.0 in April 2026.
Meta's roadmap runs from ORv3 racks with up to 72 accelerators to ORW with up to 144, then a rack above 900 kW in 2027, and AMD built its Helios rack-scale platform on ORW. Sessions cover ORW progress and validation, NVIDIA's MGX power rack reference design, and applying ORv3 and ORW design principles to Arm-based AI racks: the frame, the busbar, the liquid manifolds and the power rack that now sits beside the IT rack.
A chiplet only becomes a market when dies from different vendors can talk to each other. OCP's Bunch of Wires (BoW) 2.0 die-to-die specification now has a memory addendum, led by Eliyan, that targets HBM4 bandwidth of 2 TB/s within less than 10 mm of die edge.
Arm contributed its Foundation Chiplet System Architecture (FCSA) to OCP in October 2025, a vendor-neutral baseline for splitting a monolithic SoC into compute, memory, I/O and accelerator chiplets. The OCP Chiplet Marketplace, launched in 2024, catalogs chiplets, design tools and services. Sessions cover the open chiplet economy, scaling compute, memory and connectivity, interoperable chiplet systems on Arm Neoverse, and a common security architecture for FCSA: the groundwork for running more than one accelerator, or your own, without a single-vendor stack.
AI-native servers: modular, liquid-cooled, built around the accelerator
The server is being rebuilt around the accelerator. NVIDIA's Vera Rubin NVL72 compute tray is 100% liquid-cooled and replaces internal cables with a printed circuit board midplane, and NVIDIA plans to contribute the rack and tray designs to OCP as an open standard.
Open building blocks keep the rest of the server interchangeable. DC-MHS sets common form factors and interfaces for host processor modules, I/O and management (DC-SCM), and AMD's Helios rack uses it. OCP NIC 3.0, at v1.6 since March 2025 with a further draft in August 2026, defines the network card in four form factors (SFF, LFF, TSFF and DSFF). Sessions cover MHS modular plug-and-play tools and proof-of-concept work, the Open Adapter Card (OAC) for sub-rack-scale acceleration, and the next OCP NIC generation with liquid cooling.
Scale-up interconnect: open Ethernet inside the rack
Scale-up, the fabric that lets accelerators in a rack share memory as one machine, is moving to open Ethernet. SUE-T, the scale-up Ethernet transport from Broadcom and Arista published at OCP in October 2026, targets under 2 microseconds round trip and up to 16K XPUs in a single hop.
ESUN (Ethernet for Scale-Up Networking) launched at the 2025 OCP Global Summit with 12 founding members, among them AMD, Broadcom, Meta, Microsoft, NVIDIA and OpenAI, and has since published its 1.0 specification. ESUN covers the network side (L2/L3 framing, switching and lossless, error-resilient transfer); SUE-T covers the XPU endpoint, and in its reference example six 1.6T instances give one XPU 9.6 Tb/s of scale-up bandwidth. Sessions cover ESUN, SUE-T and MRC, an RDMA transport built for AI training networks. Scale-out between racks belongs to the Cluster track.
In-rack cooling: how far single-phase cold plate can go
Liquid is now designed into the rack, not added to the room. NVIDIA's Vera Rubin rack runs on 45°C liquid, and Rittal expects coolant flow per rack to rise from about 300 to about 2,000 liters per minute as racks head to 1 MW, through eight quick disconnects instead of two.
Flow is where single-phase cold plate runs into trouble. On a 750 kW loop, nVent and Alloy Enterprises showed that raising flow from 0.7 to 2.0 LPM per kW multiplies header pressure drop about 7x and pump power about 19x. Sessions cover where air cooling still wins for general compute, real-time monitoring of propylene glycol coolant in the technology cooling system, standardized two-phase cooling, tooling and telemetry for liquid cooling at fleet scale, and a closing panel on the runway left for single-phase cold plate before two-phase scales. CDUs and facility water belong to the Data Center track.
Topics include
Direct-to-chip cold plates
Two-phase liquid cooling
Technology cooling system (TCS)
Propylene glycol (PG25) coolant
Quick disconnects
Air vs liquid cooling
06 · In-Rack Power
In-rack power: sidecars, 800 VDC and the busbar
At 54 V, a 1 MW rack would draw about 18,500 A; at 800 V, about 1,250 A. The Mt Diablo disaggregated power rack from Google, Meta and Microsoft, published as v1.0 in October 2026, moves AC-to-DC conversion into a sidecar sized for 800 kW to 1.1 MW of IT load, with ±400 VDC or 800 VDC out.
Mt Diablo specifies 45 to 90 seconds of battery backup at full load. NVIDIA's MGX-compatible 800 VDC power rack, due in the second half of 2026, feeds 800 VDC to compute racks in an existing AC row without changes to the building's electrical system. Sessions cover aggregated and cascaded power shelf architectures, an 800 V DC sidecar design, ORv3 power for higher loads, 800 V direct-to-server power shelves, and an Open Rack busbar interface for racks of 1 MW and beyond. Power from the grid to the row belongs to the Data Center and Energy tracks.
